This invention relates to arithmetic units for use in digital computers and digital data processors for adding and subtracting binary and binary coded decimal numbers.
As is known, many present day digital computers and digital data processing machines are capable of performing decimal arithmetic as well as the more classical binary arithmetic. For many applications, particularly business and commercial type applications, there are definite advantages in using decimal arithmetic. For most data processors presently on the market, however, the performance of decimal arithmetic is very slow compared to the performance of binary arithmetic. A primary purpose of the present invention, therefore, is to provide a new and improved arithmetic unit for enabling a data processor to perform decimal arithmetic operations with significantly greater speed and, in many cases, with a speed very nearly approaching the speed for the corresponding binary arithmetic operations with operands of comparable width.
In accordance with one feature of the present invention, the speed of performing decimal operations is improved by providing an arithmetic unit which can operate directly on decimal data in zoned format and without having to first convert such data to a packed format. To fully appreciate the significance of this, it must be recognized that many present day input and output devices for supplying data to and receiving data from a data processor are constructed to transmit and receive data in the form of 8-bit binary coded characters encoded in accordance with the well-known Extended Binary Coded Decimal Interchange Code (EBCDIC). Each such 8-bit character represents one alphabetical letter or one numerical digit or one graphic symbol such as a dollar sign, semicolon, etc. For the case of a numerical character, the higher order four bits are called a zone field and the lower order four bits are called a digit field. The coding for the 4 bits in the zone field is 1111 if the 4 bits in the digit field represent a decimal digit in eight-four-two-one binary coded decimal form. Numerical data having this 8-bit zone/digit construction for each numerical character is said to be in zoned format. As is apparent, only the 4-bit digit fields are of interest for purposes of performing arithmetic computations.
Since the numerical data from the input device is usually coming into the data processor in zoned decimal format; it would be desirable to be able to supply zoned decimal numbers to the arithmetic unit, perform the desired addition or subtraction with such zoned decimal numbers and end up with zoned decimal answers which can be sent to one or more output devices without need for any further special treatment. Unfortunately, this is not possible with most present day data processors. The presence of the zone field bits in the arithmetic unit would mess up the arithmetic computation.
In most present day data processors, what is actually done is to convert the zoned decimal numerical data into a packed decimal format before performing the arithmetic computation. This is accomplished by stripping off the zone field bits and using only the digit field bits. Afte performing the desired arithmetic operation, the resultant data must then be converted back into the zoned format before it is sent to an output device. This converting back is called "unpacking. This packing and unpacking procedure is time consuming. The present invention elimination the need for same. The present invention provides an arithmetic unit which will accept numercial data in zoned decimal format as a valid input, perform the desired decimal operation, and output the result in zone chemical format.
There has been at least one previous proposal for providing an arithmetic unit which can operate with zoned decimal data. This proposal is set forth in U.S. Pat. No. 3,752,394, granted Aug. 14, 1973, entitled "Modular Arithmetic and Logic Unit" and assigned to International Business Machines Corporation of Armonk, New York. This patent describes an arithmetic unit wherein the arithmetic operations are performed by a one-byte or eight-bit borrow look-ahead subtractor. When handling zoned decimal numerical characters, the borrow look-ahead circuitry is internally modified so that the borrow look-ahead circuits for the zone field bits are bypassed and the borrow-out signal for the highest order digit field bit is used as the borrow-out signal for the character or byte as a whole. Presumably, when adding or subtracting multidigit zoned decimal numbers, the individual zoned digits for successively higher order digit positions are added or subtracted during successive machine cycles, with the character borrow-out for one machine cycle being saved and used as the character borrow-in for the next machine cycle. In such case, the bypassing of the zone field borrow look-ahead stages prevents the zone fields from messing up the computation. This is accomplished, however, with some sacrifice in speed. In particular, the circuits which enable the bypassing of the zone field stages introduce two stages of delay per character or byte. By contrast, an arithmetic unit constructed in accordance with the present invention avoids this type of delay and hence is better suited for handling multibyte or multidigit zoned chemical numbers. Also, the present invention enables all the digits of two multidigit zoned decimal numbers to be added or subtracted during one and the same machine cycle, provided, of course, that the widths of the numbers do not exceed the data flow width of the arithmetic unit.
In accordance with another feature of the invention, the speed of decimal operations is further improved by providing an arithmetic unit having built therein the necessary hardware for knowing when to "subtract" even though the program instruction says to "add" and vice versa. The problem arises because the decimal numbers being processed may be either positive or negative numbers. Consequently, to add two decimal numbers together, it is not as simple as presenting two input numbers of operands to the arithmetic unit and simply telling such arithmetic unit to "add." The decimal numbers are represented in true magnitude form with the sign position specifying whether the operand is positive or negative. Therefore, if an add operation is desired and one operand is positive while the other is negative, the arithmetic unit should perform a subtraction operation to calculate a correct result in true magnitude form. Conversely, if a subtract operation were desired with operands of different signs, the arithmetic unit should perform an add operation to obtain the correct output.
The majority of present day general purpose data processing machines are of the microprogrammed or microcoded type. In such machines, this sign interpretation for decimal operands is done by microcode branching prior to the actual arithmetic unit operation and the signs are masked off before entering the arithmetic unit. Likewise, the preferred resultant sign is reinserted by the microcode after the arithmetic unit operation. The arithmetic unit hardware acts as a slave to the microprogrammed instructions and is presented only valid decimal digit codes with the sign codes having previously been removed.
To perform each of these decimal sign handling functions in microcode, many microwords are executed for each decimal arithmetic operation and thus the performance of a decimal operation as compared to a binary operation is very slow. A significant feature of the present invention is the provision of a hardware mechanism for enabling the arithmetic unit itself to automatically perform the correct arithmetic operation, thus eliminating the need for the various previously used and time consuming microcode steps.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.